echo "
set -tmpdir $BUILD_DIR/xst/projnav.tmp
set -xsthdpdir $BUILD_DIR/xst
run
-ifn $PRJ_FILE
-ifmt mixed
-ofn $NGC_FILE
-ofmt NGC
-p $FULL_FPGA_NAME
-top $PROJ
-opt_mode Speed
-opt_level 1
-iuc NO
-lso $LSO_FILE
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-use_dsp48 auto
-iobuf NO
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
-vlgincdir {$BUILD_DIR $FW_SRC_DIR}             
"
